Plasma etch technologies for the development of ultra-small feature size transistor devices

D Borah (1, 2) , M T Shaw (1, 2) , S Rasappa (1, 2) , R A Farrell (1, 2) , C O'Mahony (1, 2) , C M Faulkner (1, 2) , M Bosea (1, 2) , P Gleeson (1, 2) , J D Holmes (1, 2) , M A Morris (1, 2)

1 Department of Chemistry
2 CRANN

The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred ' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc.) and chemistry (etch gases, flows, interactions with substrates, etc.). In this article, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers which micro-phase separate in various conditions. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data is presented which shows that highly regular nanowires patterns of feature size below 20 nm can be created using etch optimisation techniques and in this article we demonstrate generation of crystalline silicon nanowire arrays with feature sizes as below 8 nm. Block copolymer techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity from in these nanoscale resits patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing.

Mots clés: Plasma etch; reactive ion etching; inductively coupled plasma; block copolymer lithography; feature size; pattern transfer

D Borah, M T Shaw, S Rasappa, R A Farrell, C O'Mahony, et al.. Plasma etch technologies for the development of ultra-small feature size transistor devices. Journal of Physics D: Applied Physics, 2011, 44 (17), pp.174012. ⟨10.1088/0022-3727/44/17/174012⟩. ⟨hal-00613274⟩