Full-parallel architecture for turbo decoding of product codes

Christophe Jego (1, 2, 3) , Patrick Adde (1, 2, 3) , Camille Leroux (4)

1 ELEC - Département Electronique
2 TAMCIC - Traitement Algorithmique et Matériel de la Communication, de l'Information et de la Connaissance
3 PRACOM - Pôle de Recherche Avancée en Communications
4 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)

A full-parallel architecture for turbo decoding, which achieves ultra high data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed Solomon component codes. The major advantage of our architecture is that it enables the memory blocks between all half-iterations to be removed. Moreover, the latency of the turbo decoder is strongly reduced. In fact, the proposed architecture opens the way to numerous applications such as optical transmission and data storage. In particular, our block turbo decoding architecture can support optical transmission at data rates above 10 Gb/s.

Domaines: Electronique

Christophe Jego, Patrick Adde, Camille Leroux. Full-parallel architecture for turbo decoding of product codes. Electronics Letters, 2006, 42 (18), pp.1052 -1053. ⟨10.1049/el:20062168⟩. ⟨hal-00538604⟩