EMI Modeling of Integrated Circuits using pattern simulation
Résumé
Due to the increasing speed and the low voltage supply of CMOS processes, Integrated Circuits (ICs) are more and more confronted to ElectroMagnetic Compatibility (EMC) problems. Noise emission is propagated through ICs by coupling, routing capacitors and package parasitics. These effects often leads to signal integrity failures, and noise emission level overruns. To study this effect at chip level, from specifications to layout finishing, a new noise simulation has been developped in order to be fast and accurate. Then some comparisons have been made with standard spice simulations showing the efficiency of this flow.
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