A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2009

A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs

Résumé

In this study, a new technique to extract the S/D series resistance (Rsd) from the total resistance versus transconductance gain plot Rtot(1/beta) is proposed. The technique only requires the measurement of Id(Vgs)|Vgt and beta, allowing fast and statistical analysis in an industrial context. Unlike the usual Rtot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for Rsd(Vgs) and the effective mobility reduction factor mueff(Vgt)/mueff(0).
Fichier principal
Vignette du fichier
VLSI-TSA_4_0.pdf (103.45 Ko) Télécharger le fichier
T85_Dominique_Fleury_1.pdf (819.79 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Format : Autre

Dates et versions

hal-00465769 , version 1 (21-03-2010)

Identifiants

Citer

Dominique Fleury, Antoine Cros, Grégory Bidal, Hugues Brut, Emmanuel Josse, et al.. A New Technique to Extract the Gate Bias Dependent S/D Series Resistance of Sub-100nm MOSFETs. International Symposium on VLSI Technology, Systems and Applications, Apr 2009, Hsinchu, Taiwan. pp.109 - 110, ⟨10.1109/VTSA.2009.5159314⟩. ⟨hal-00465769⟩
116 Consultations
489 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More