On-chip Processor Traffic Modeling for NoC Design
Abstract
We propose a chapter focused on multi-processor system on chip (MPSoC) traffic modeling for embedded computing systems (telecommunication and multimedia mainly). The chapter will be based on the knowledge acquired during the PhD of Antoine Scherrer [4] entitled "Statistical analysis of on chip communications". Our experience shows that, while it is possible to emulate quite precisely the traffic generated by a dedicated ip, it is much more difficult to emulate the traffic produced by processors associated with caches. Hence, we will concentrate on the efficient analysis and synthesis on on-chip traffic generated by processors ip. We will review the dierent techniques used for NoC traffic modeling and we will insist on two points for future traffic generators: the use of advanced statistical models (i.e. second order statistics) and the use of multi-phase trac (i.e. piece-wise stationary models). The chapter will be illustrated by performance results of a multi-phase trac generator used in a cycle accurate MPSoC simulator based on systemC [2].