Some Progress in the Symbolic Verification of Timed Automata

Marius Bozga (1) , Oded Maler (1) , Amir Pnueli (2) , Sergio Yovine (1)

1 VERIMAG - IMAG - VERIMAG
2 Department of Computer Science and Applied Mathematics [Rehovot]

In this paper we discuss the practical difficulty of analyzing the behavior of timed automata and report some results obtained using an experimental BDD-based extension of KRONOS. We have treated examples originating from timing analysis of asynchronous boolean networks and CMOS circuits with delay uncertainties and the results outperform those obtained by previous implementation of timed automata verification tools.

Keywords: timed automata; BDDs; NDDs; symbolic verification; circuit analysis

Domains: Embedded Systems

Marius Bozga, Oded Maler, Amir Pnueli, Sergio Yovine. Some Progress in the Symbolic Verification of Timed Automata. Computer Aided Verification 9th International Conference, CAV'97, Jun 1997, Haifa, Israel. pp.179--190, ⟨10.1007/3-540-63166-6_19⟩. ⟨hal-00374086⟩