A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs

Fabienne Nouvel (1) , Florent Berthelot (2) , Dominique Houzet (3)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 IETR - Institut d'Electronique et de Télécommunications de Rennes
3 GIPSA-GPIG - GIPSA - Géométrie, Perception, Images, Geste

Reconfigurable computing is certainly one of the most important emerging research topics on digital processing architectures over the last few years. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose, we present an automatic design generation methodology for heterogeneous architectures based on DSPs and FPGAs that ease and speed RTR implementation. We focus on how to take into account specificities of partially reconfigurable components from a high-level specification during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of an FPGA with automatic management of the reconfiguration process. Furthermore, this automatic design generation enables a reconfiguration prefetching technique to minimize reconfiguration latency and buffer-merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. This implementation example illustrates the benefits of the proposed design methodology.

Domaines: Electronique

Fabienne Nouvel, Florent Berthelot, Dominique Houzet. A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs. EURASIP Journal on Embedded Systems, 2008, 2008, pp.ID 793919. ⟨10.1155/2008/793919⟩. ⟨hal-00320192⟩