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2008 Joint IEEE-NEWCAS and TAISA Conference, Montréal : Canada (2008)
SystemC/TLM Semantics for Heterogeneous System-on-Chip Validation
Florence Maraninchi ( ) 1, Matthieu Moy 1, Jérôme Cornet 1, 2, Laurent Maillet-Contoz 3, Claude Helmstetter 1, 4, 5, Claus Traulsen 6
(2008-06)

SystemC has become a de facto standard for the system-level description of systems-on-a-chip. SystemC/TLM is a library dedicated to transaction level modeling. It allows to define a virtual prototype of a hardware platform, on which the embedded software can be tested. Applying formal validation techniques to SystemC descriptions of SoCs requires that the semantics of the language be formalized. The model of time and concurrency underlying the SystemC definition is intermediate between pure synchrony and pure asynchrony. We list the available solutions for the semantics of SystemC/TLM, and explain how to connect SystemC to existing formal validation tools.
1:  VERIMAG (VERIMAG - IMAG)
CNRS : UMR5104 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)
2:  STMicroelectronics (Grenoble) (ST-GRENOBLE)
STMicroelectronics
3:  STMicroelectronics (Crolles) (ST-CROLLES)
STMicroelectronics
4:  Laboratoire Franco-Chinois d'Informatique, d'Automatique et de Mathématiques Appliquées (LIAMA)
Institute of Automation, Chinese Academy of Sciences – Chinese Academy of Science (CAS) – INRA – INRIA – CIRAD – CNRS
5:  FORMES (LIAMA)
INRIA – Tsinghua University / Beijing – LIAMA
6:  Informatic Kiel University
Christian-Albrechts-Universität zu Kiel
Synchronous languages, applications and programming
Computer Science/Embedded Systems

Computer Science/Modeling and Simulation

Computer Science/Computation and Language
SystemC – TLM – lustre – spin – promela – semantics – model-checking – verification – model – SoC – System-on-a-Chip
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