Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm

Wladyslaw Szczesniak (1)

1 Faculty of Electronics, Telecommunications and Informatics

This paper presents a BPD (Balanced Power Dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.

Mots clés: Package reliability

Domaines: Science des matériaux [cond-mat.mtrl-sci]

Wladyslaw Szczesniak. Reducing Average and Peak Temperatures of VLSI CMOS Digital Circuits by Means of Heuristic Scheduling Algorithm. THERMINIC 2007, Sep 2007, Budapest, Hungary. pp.220-225. ⟨hal-00202564⟩