Temperature Gradient Alleviating Method for Arithmetic Units

R. Egawa (1) , M. Ito (1) , N. Hasegawa (1) , T. Nakamura (1)

1 Graduate School of Information Sciences

Recently, thermal-aware digital circuit design in advanced technologies is great challenges to realize high-speed and robust microprocessors. In this paper, we explore temperature gradient alleviating method for arithmetic units. Aiming at alleviating temperature gradients at logical circuit design level, we try to flatten out a power density by applying delay-balancing technique for equal-delay circuits. Our proposal is evaluated in fine grain thermal simulation. Simulation results show the strong dependency between placement and temperature gradients on arithmetic units.

Mots clés: Thermal-aware circuit design; delay balancing logical effort; fine grain thermal simulation

Domaines: Architectures Matérielles [cs.AR]

R. Egawa, M. Ito, N. Hasegawa, T. Nakamura. Temperature Gradient Alleviating Method for Arithmetic Units. THERMINIC 2005, Sep 2005, Belgirate, Lago Maggiore, Italy. pp.151-156. ⟨hal-00189468⟩