Thermal-aware design rules for nanometer ICs

J.-L. Rossello (1) , S. Bota (1) , M. Rosales (1) , A. Keshavarzi (2) , J. Segura (2)

1 Electronic Technology Group
2 Microprocessor Research Labs.

The ever-aggressive increase in performance and integration of CMOS ICs is leading to higher power dissipation and power density, with a consequent increase of the circuit junction temperature together with the generation of non-uniform thermal maps and hot-spots. Moreover, it has been predicted that technology scaling will bring static power to a significant fraction of the total power, complicating further this analysis due to the exponential dependence of leakage with temperature. This scenario represents an important challenge in circuit design due to the lack of accurate and compact thermal models capable of describing not only the impact of non-uniform thermal maps on circuit performance, but also on static leakage for an accurate power modeling. In this paper we analyze the influence of considering the leakage power contribution to the circuit thermal map and therefore on its overall power dissipation and performance. Based on the analysis of two key thermal parameters (the mean and the maximum junction temperatures) we derive design guidelines to reduce the impact of hot-spots on circuit performance and reliability using an entropy-based cost function for thermal optimization.

Mots clés: Thermal-aware design; circuit modeling

Domaines: Architectures Matérielles [cs.AR]

J.-L. Rossello, S. Bota, M. Rosales, A. Keshavarzi, J. Segura. Thermal-aware design rules for nanometer ICs. THERMINIC 2005, Sep 2005, Belgirate, Lago Maggiore, Italy. pp.1-6. ⟨hal-00189444⟩