A Constraint Network Based Approach to Memory Layout Optimization

G. Chen (1) , M. Kandemir (1) , M. Karakoy (2)

1 Computer Science and Engineering Department
2 Dept. of Computing

While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking dependences (legality issues) and transformation of all of the array references within the loop body indiscriminately (while some of the references can benefit from the transformation, others may not). As a result, data transformations, i.e., transformations that modify memory layout of array data instead of loop structure have been proposed. One of the problems associated with data transformations is the difficulty of selecting a memory layout for an array that is acceptable to the entire program (not just to a single loop). In this paper, we formulate the problem of determining the memory layouts of arrays as a constraint network, and explore several methods of solution in a systematic way. Our experiments provide strong support in favor of employing constraint processing, and point out future research directions.

Domaines: Architectures Matérielles [cs.AR]; Electronique

G. Chen, M. Kandemir, M. Karakoy. A Constraint Network Based Approach to Memory Layout Optimization. DATE'05, Mar 2005, Munich, Germany. pp.1156-1161. ⟨hal-00181684⟩