A Time Slice Based Scheduler Model for System Level Design

Luciano Lavagno (1) , Claudio Passerone (1) , Vishal Shah (1) , Yosinori Watanabe (2)

1 Dept. of Electronics
2 Cadence Research Laboratories

Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important requirement in the design flow of Embedded Systems. Time-to-market, faster upgradability and flexibility are some of the driving points to put increasing amounts of functionality as software executed on general purpose processing elements. In this scenario, dividing a monolithic task into multiple interacting tasks, and scheduling them on limited processing elements has become very important for a system designer. This paper presents an approach to model time-slice based task schedulers in the designs where the performance estimate of hardware and software models is less than time-slice accurate. The approach aims to increase the simulation efficiency of designs modeled at system level. We used Metropolis as our codesign environment.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe. A Time Slice Based Scheduler Model for System Level Design. DATE'05, Mar 2005, Munich, Germany. pp.378-383. ⟨hal-00181543⟩