Leakage-Aware Interconnect for On-Chip Network

Yuh-Fang Tsai (1) , Vijaykrishnan Narayaynan (1) , Yuan Xie (1) , Mary Jane Irwin (1)

1 Computer Science and Engineering

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Yuh-Fang Tsai, Vijaykrishnan Narayaynan, Yuan Xie, Mary Jane Irwin. Leakage-Aware Interconnect for On-Chip Network. DATE'05, Mar 2005, Munich, Germany. pp.230-231. ⟨hal-00181520⟩