Specification Test Compaction for Analog Circuits and MEMS

Sounil Biswas (1) , Peng Li (2) , R. D. (shawn) Blanton (3) , Larry T. Pileggi (3)

1 dept. of Electrical and Computer Engineering
2 Dept. of EE
3 Dept. of EE

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required. We propose to eliminate redundant tests by employing e-SVM based statistical learning. Application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests with negligible error. Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 0.6% and 0.9%, respectively. For the accelerometer, defect escape of 0.2% and yield loss of 0.1% occurs when the hot and colt tests are eliminated. For the accelerometer, this level of Compaction would reduce test cost by more than half.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Sounil Biswas, Peng Li, R. D. (shawn) Blanton, Larry T. Pileggi. Specification Test Compaction for Analog Circuits and MEMS. DATE'05, Mar 2005, Munich, Germany. pp.164-169. ⟨hal-00181510⟩