Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing

Fang Liu (1) , Jacob J. Flomenberg (1) , Devaka V. Yasaratne (1) , Sule Ozev (1)

1 Dept. of EE

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this paper, we present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev. Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. DATE'05, Mar 2005, Munich, Germany. pp.126-131. ⟨hal-00181505⟩