Evaluation of Error-Resilience for Reliable Compression of Test Data

Hamidreza Hashempour (1) , Luca Schiano (2) , Fabrizio Lombardi (3)

1 LTX Corp., San Jose
2 Dept. of Electrical and Computer Engineering [Northeastern]
3 Northeastern University [Boston]

This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the Device-Under-Test (DUT)). In an ATE, bit-flips may occur in either the electronics components of the loadboard, or the high speed serial communication links (between the user interface workstation and the head). It is shown that errors caused by bit-flips can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The effects of bit-flips on compression are analyzed and various test data compression techniques are evaluated. It is shown that for benchmark circuits, coverage of test sets can be reduced by 10%-30%.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi. Evaluation of Error-Resilience for Reliable Compression of Test Data. DATE'05, Mar 2005, Munich, Germany. pp.1284-1289. ⟨hal-00181305⟩