A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching

Y. Satish Kumar (1) , Jun Li (1) , Claudio Talarico (1) , Janet Wang (1)

1 ECE

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Wang. A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching. DATE'05, Mar 2005, Munich, Germany. pp.770-775, ⟨10.1109/DATE.2005.31⟩. ⟨hal-00181207⟩