Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver

M. K. Iyer (1) , G. Parthasarathy (1) , K.-T. Cheng (1)

1 Dept of Electrical and Computer Engineering

We present new techniques for improving search in a hybrid Davis-Putnam-Logemann-Loveland based constraint solver for RTL circuits (HDPLL). In earlier work on HDPLL, the authors combined solvers for integer and Boolean domains using finite-domain constraint propagation with heuristic conflict-based learning. In this work, we describe a new algorithm that extends the conflict-based unique-implication point learning in Boolean SAT solvers to hybrid Boolean-Integer domains in HDPLL. We describe data-structures for efficient constraint propagation on the hybrid learned relations, similar to two-literal watching in Boolean SAT. We demonstrate that these new techniques provide considerable performance benefits when compared with other combinations of decision theories.

Domaines: Architectures Matérielles [cs.AR]; Electronique

M. K. Iyer, G. Parthasarathy, K.-T. Cheng. Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver. DATE'05, Mar 2005, Munich, Germany. pp.666-671. ⟨hal-00181184⟩