Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation

Florent Berthelot (1) , Fabienne Nouvel (1)

1 IETR - Institut d'Electronique et de Télécommunications de Rennes

Dynamic and partial reconfiguration of FPGAs enables systems to adapt to changing demands. This paper concentrates on how to take into account specificities of partially reconfigurable components during the high level Adequation Algorithm Architecture process. We present a method which generates automatically the design for both partially and fixed parts of FPGAs.

Florent Berthelot, Fabienne Nouvel. Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation. Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Mar 2006, Karlsruhe, Germany. pp.436 - 437, ⟨10.1109/ISVLSI.2006.71⟩. ⟨hal-00020195⟩