An SFS Berger check prediction ALU and its application to self-checking processor designs

Lo Jien-Chung (1) , S. Thanawastien (1) , T.-R.-N. Rao (1) , M. Nicolaidis (2, 3)

1 DEPT. OF ELECTR. & COMPUT. ENG., RHODE ISLAND UNIV. - Dept. of Electr. & Comput. Eng., Rhode Island Univ.
2 IROC TECHNOLOGIES - iROc Technologies
3 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed.

Mots clés: fault-models; BIST-; Berger-check-prediction; self-checking-processor-designs; strongly-fault-secure; error-models; VLSI-ALU; self-testing; Berger-code

Domaines: Micro et nanotechnologies/Microélectronique

Lo Jien-Chung, S. Thanawastien, T.-R.-N. Rao, M. Nicolaidis. An SFS Berger check prediction ALU and its application to self-checking processor designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992, April ; 11(4), pp.525-40. ⟨10.1109/43.125100⟩. ⟨hal-00014032⟩