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| HAL : hal-00008030, version 1 |
| Fiche détaillée |  Récupérer au format |
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| (1993) |
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| DLS: A scheduling algorithm for high-level synthesis in VH |
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| K. O'Brien 1M. Rahmouni 1 |
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| (1993) |
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| Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL is presented. It compares favorably with results produced by other control-flow oriented approaches such as path-based scheduling, but avoids the path explosion problem. In addition, the VHDL accepted by the scheduler is quite comprehensive, including nested branches, loops (whose conditions can be compounded), loop exit statements and procedure calls. The algorithm forms an integral part of the AMICAL data-path compiler. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| dynamic-loop-scheduling – scheduling-algorithm – high-level-synthesis – VHDL- – control-flow-dominated-designs – nested-branches – loop-exit-statements – procedure-calls – AMICAL-data-path-compiler |
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| hal-00008030, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00008030 | |
| oai:hal.archives-ouvertes.fr:hal-00008030 | |
| Contributeur : Lucie Torella | |
| Soumis le : Vendredi 19 Août 2005, 09:40:33 | |
| Dernière modification le : Vendredi 19 Août 2005, 09:40:33 | |
