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Habilitation à diriger des recherches

Logical Time in Model-Driven Engineering

Abstract : ccsl has arisen from different inspiring models in an attempt to abstract away the data and the algorithms and to focus on events and control. Even though CCSL was initially defined as the time model of the UML profile for MARTE, it has now become a full-edged domain-specific modeling language for capturing causal, chronological and timed relationships. It is intended to be used as a complement of other syntactic models that capture the data structure, the architecture and the algorithm. This work starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSLis introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, we discuss an observer-based technique to verify implementations in different languages (Esterel, VHDL) against a CCSL specification.
Keywords : Logical Time
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Habilitation à diriger des recherches
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Contributor : Frédéric Mallet <>
Submitted on : Sunday, April 28, 2019 - 6:09:03 PM
Last modification on : Monday, October 12, 2020 - 10:30:40 AM


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  • HAL Id : tel-02113377, version 1



Frédéric Mallet. Logical Time in Model-Driven Engineering. Embedded Systems. Université Nice Sophia Antipolis, 2010. ⟨tel-02113377⟩



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