86 5.2.1 Principle, 86 5.2.2 Link with the Kahn Process Network Model, p.86 ,
91 5.4.1 Lock-Free Programming, p.93 ,
117 6.5.1 SycView Measurements, p.118 ,
Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013. ,
DOI : 10.7873/DATE.2013.017
URL : https://hal.archives-ouvertes.fr/hal-00761047
Validation de Modèles de Systèmes sur Puce en Présence d'Ordonnancements Indéterministes et de Temps Imprécis, 2007. ,
Techniques et Outils pour la Vérification de Systèmes-sur-Puce au Niveau Transaction, 2005. ,
Séparation des Aspects Fonctionnels et non-Fonctionnels dans les Modèles Transactionnels des Systèmes sur Puce, 2008. ,
Contributions to the Transaction-Level Modeling of Systems-ona-Chip, 2011. ,
Accélération des Simulations de Systèmes sur Puce au Niveau Transactionnel, Diplôme de Recherche Technologique (DRT), 2007. ,
High-Level Synthesis: Past, Present, and Future, IEEE Design & Test of Computers, vol.26, issue.4, pp.18-25, 2009. ,
DOI : 10.1109/MDT.2009.83
A brief introduction on contemporary High-Level Synthesis, 2014 IEEE International Conference on IC Design & Technology, pp.1-4, 2014. ,
DOI : 10.1109/ICICDT.2014.6838614
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis, 2015 33rd IEEE International Conference on Computer Design (ICCD), pp.475-478, 2015. ,
DOI : 10.1109/ICCD.2015.7357152
Is high level synthesis ready for business? A computational finance case study, 2014 International Conference on Field-Programmable Technology (FPT), pp.12-19, 2014. ,
DOI : 10.1109/FPT.2014.7082747
What input-language is the best choice for high level synthesis (HLS)?, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.857-858, 2010. ,
DOI : 10.1145/1837274.1837489
SycView: Visualize and Profile SystemC Simulations, Workshop on Design Automation for Understanding Hardware Designs, 2016. ,
URL : https://hal.archives-ouvertes.fr/hal-01295282
Challenges for the parallelization of loosely timed SystemC programs, 2015 International Symposium on Rapid System Prototyping (RSP), p.2015 ,
DOI : 10.1109/RSP.2015.7416547
URL : https://hal.archives-ouvertes.fr/hal-01214891
Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study, Electronics, vol.7, issue.4, p.22, 2016. ,
DOI : 10.1016/j.micpro.2015.06.001
URL : https://hal.archives-ouvertes.fr/hal-01321055
Efficient Automatic Visualization of SystemC Designs, FDL, pp.646-658, 2003. ,
SystemCXML: An Extensible SystemC Front end Using XML, FDL, pp.405-409, 2005. ,
A Loosely-Coupled Graphical User Interface for Run-Time Control of SystemC Simulation Models, IJSSST, 2006. ,
System Exploration of SystemC Designs, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006. ,
DOI : 10.1109/ISVLSI.2006.87
Visualization of SystemC Designs, 2007 IEEE International Symposium on Circuits and Systems, pp.413-416, 2007. ,
DOI : 10.1109/ISCAS.2007.378551
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016. ,
DOI : 10.1109/VLSID.2016.45
Parallel Discrete-Event Simulation, 2010. ,
DOI : 10.1177/003754979907200309
A clustered manycore processor architecture for embedded and accelerated applications, 2013 IEEE High Performance Extreme Computing Conference (HPEC), pp.1-6, 2013. ,
DOI : 10.1109/HPEC.2013.6670342
A Conservative Approach to SystemC Parallelization, Computational Science, pp.653-660, 2006. ,
DOI : 10.1007/11758549_89
parSC, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, pp.241-246, 2010. ,
DOI : 10.1145/1878961.1879005
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp.250-257, 2014. ,
DOI : 10.1109/SAMOS.2014.6893218
SCGPSim: A fast SystemC simulator on GPUs, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.149-154, 2010. ,
DOI : 10.1109/ASPDAC.2010.5419903
Optimized Out-of-Order Parallel Discrete Event Simulation Using Predictions, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp.3-8, 2013. ,
DOI : 10.7873/DATE.2013.016
Hybrid analysis of SystemC models for fast and accurate parallel simulation, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp.226-231, 2017. ,
DOI : 10.1109/ASPDAC.2017.7858324
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures, Microprocessors and Microsystems, vol.39, issue.8, pp.1063-1075, 2015. ,
DOI : 10.1016/j.micpro.2015.06.001
Relaxing Synchronization in a Parallel SystemC Kernel, 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008. ,
DOI : 10.1109/ISPA.2008.124
URL : https://hal.archives-ouvertes.fr/hal-01428323
SAGA, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.115-120, 2012. ,
DOI : 10.1145/2228360.2228382
An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006. ,
DOI : 10.1109/DATE.2006.244003
URL : https://hal.archives-ouvertes.fr/hal-01338224
Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations, Design, Automation and Test in Europe (DATE), pp.606-609, 2010. ,
URL : https://hal.archives-ouvertes.fr/hal-00748083
A systemc TLM framework for distributed simulation of complex systems with unpredictable communication, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), pp.1-8, 2011. ,
DOI : 10.1109/DASIP.2011.6136847
Optimistic Parallelisation of SystemC Master's thesis, 2011. ,
Distributed, loosely-synchronized systemC/TLM simulations of many-processor platforms, Proceedings of the 2014 Forum on Specification and Design Languages (FDL), pp.978-980, 2014. ,
DOI : 10.1109/FDL.2014.7119360
Dietmar Petras, and Hoffmann Andreas. legaSCi: Legacy SystemC Model Integration into Parallel SystemC Simulators, Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems Proceedings of Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), pp.2188-2193, 2013. ,
Time-Decoupled Parallel SystemC Simulation, Design, Automation and Test in Europe (DATE), pp.1-191, 2014. ,
DOI : 10.7873/date.2014.204
Parallel SystemC simulation for ESL design using flexible time decoupling, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp.378-383, 2015. ,
DOI : 10.1109/SAMOS.2015.7363702
SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments, Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016. ,
DOI : 10.3850/9783981537079_0114
Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models, Proceedings of the 14th ACM Great Lakes symposium on VLSI, pp.248-253, 2004. ,
Parallel and Distributed Simulation, Winter Simulation Conference (WSC), pp.45-59, 2015. ,
Conservative Distributed Discrete Event Simulation with SystemC using Explicit Lookahead. Digital Force White Paper, 2004. ,
A New Parallel SystemC Kernel Leveraging Manycore Architectures, Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016. ,
DOI : 10.3850/9783981537079_0325
Out-of-Order Parallel Simulation for ESL Design, Design, Automation and Test in Europe (DATE), pp.141-146, 2012. ,
May-Happen-in-Parallel Analysis based on Segment Graphs for Safe ESL Models, Design, Automation and Test in Europe (DATE), pp.1-6, 2014. ,
Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs, 17th Asia and South Pacific Design Automation Conference, pp.455-460, 2012. ,
DOI : 10.1109/ASPDAC.2012.6164991
SystemC simulation on GP-GPUs, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '12, 2012. ,
DOI : 10.1145/2380445.2380500
jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip, 2011 Design, Automation & Test in Europe, 2011. ,
DOI : 10.1109/DATE.2011.5763309
Multi-core parallel simulation of System-level Description Languages, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011. ,
DOI : 10.1109/ASPDAC.2011.5722205
Parallel discrete event simulation of Transaction Level Models, 17th Asia and South Pacific Design Automation Conference, pp.227-231, 2012. ,
DOI : 10.1109/ASPDAC.2012.6164949
Cloning parallel simulations, ACM Transactions on Modeling and Computer Simulation, vol.11, issue.4, pp.378-407, 2001. ,
DOI : 10.1145/508366.508370
URL : http://www.cs.uga.edu/~maria/pads/papers/hybinette-tomacs-2000.pdf
The Semantics of a Simple Language for Parallel Programming, Information Processing, vol.74, pp.471-475, 1974. ,
Bounded Scheduling of Process Networks, 1995. ,
Lock-Free Data Structures, C/C++ User Journal, 2004. ,
Correct and Efficient Bounded FIFO Queues, 2013 25th International Symposium on Computer Architecture and High Performance Computing, pp.144-151, 2013. ,
DOI : 10.1109/SBAC-PAD.2013.8
Light64, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, pp.541-552, 2009. ,
DOI : 10.1145/1669112.1669180
Efficient Mutation Testing of Multithreaded Code. Software Testing, Verification and Reliability, pp.375-403, 2013. ,
Dekker's Mutual Exclusion Algorithm Made RW-Safe. Concurrency and Computation: Practice and Experience, pp.144-165, 2016. ,
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), International Conference on, pp.308-317, 2009. ,
DOI : 10.1145/334012.334015
High-Level Synthesis Blue Book. Xlibris Corporation, 2010. ,
Requirements on the Execution of Kahn Process Networks, pp.319-334, 2003. ,
DOI : 10.1007/3-540-36575-3_22
Evolution of Wireless Sensor Networks Towards the Internet of Things: A Survey, SoftCOM 2011, 19th International Conference on Software, Telecommunications and Computer Networks, pp.1-6, 2011. ,
IoT design space challenges: Circuits and systems, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, pp.1-2, 2014. ,
DOI : 10.1109/VLSIT.2014.6894411
URL : http://web.eecs.umich.edu/~prabal/pubs/papers/blaauw14iot.pdf
The Internet of Things vision: Key features, applications and open issues, Computer Communications, vol.54, 2014. ,
DOI : 10.1016/j.comcom.2014.09.008
Principes et Réalisation d'une Interface de Synchronisation Interopérable entre Modèles de Calcul SystemC AMS pour le Prototypage Virtuel Optimisé de Systèmes Multi-Disciplines, p.2016 ,
Principes et Réalisation d'un Environnement de Prototypage Virtuel de Systèmes Hétérogènes Composables, École doctorale informatique , télécommunications et électronique, p.2017 ,
Development and Implementation of a MotionJPEG Capable JPEG Decoder in Hardware, 2008. ,