Fault-mitigation strategies for reliable FPGA architecture

Abstract : Reconfigurable Field Programmable Gate Arrays (FPGAs) are extensively employed in various application domains due to their flexibility, high–density functionality, high performance and low–cost development compared to ASICs (Application Specific Integrated Circuits). However, the challenge that must be tackled during system design is their high susceptibility to the radiation induced faults such as Single Event Effects (SEEs). These radiation induced faults are a major concern in safety and mission critical systems such as automotive and avionics systems. In general, most of today’s commercial off-the shelf (COTS) FPGAs are not designed to work under these harsh environments, except for specific circuits that have been radiation– hardened at the fabrication process level, but at a very high cost overhead, which makes them less interesting from an economic and performance point of view. Design based techniques and architectural customization are the other ways to achieve desired level of reliability in a system design. This thesis work is a part of a multi-partner project–ARDyT, which aims to develop a low–cost reliable FPGA architecture with supporting EDA tool-suite that offers a complete environment for a fault tolerant system design. The ARDyT FPGA architecture plans to incorporate appropriate fault mitigation strategies at different level of the architecture. The work carried-out in this thesis focus mainly on developing reliability strategies at hardware and configuration level. A fault-aware customized configurable logic block architecture is proposed to support fault mitigation process in configurable logic resources. One of the main objectives of ARDyT project is to handle multi-bit upsets (MBUs) in the configuration bitstream. A new built–in 3–Dimensional Hamming (3DH) error correcting scheme is proposed to handle MBUs in the configuration bitstream. Proposed schemes are made adaptable in such a way that they are integrated in the ARDyT architectural framework to support the global (centralized) reliability management strategy.
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  • HAL Id : tel-01590352, version 1

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Chagun Basha Basheer Ahmed. Fault-mitigation strategies for reliable FPGA architecture. Signal and Image processing. Université Rennes 1, 2016. English. ⟨tel-01590352⟩

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