Un modèle de structure de données Cache-aware pour un parallélisme et un équilibrage dynamique de la charge

Marwa Sridi 1, 2
1 DATAMOVE - Data Aware Large Scale Computing
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
Abstract : Scientific and industrial applications that need high computational performance to be used are always facing a processing time issue. One of the procedures to deal with this issue is managing properly data in order to take full advantage of the shared memory specifications of the computing platforms. Our claim is to exploit the techniques of parallelism adapted to multi-level loops in order to ensure memory locality. In this report, we propose a new organization of the data structure for FEM based simulation codes that require interesting speedups. We applied our approach on the industrial fast transients simulator EUROPLEXUS. Experiments on various datasets show that our approach is efficient for the cache use since it reduces the execution time by around 40% for a well-defined data group size. Our approach consists on the implementation of an outer level loop around the main loop iterating on the simulation elements. The outer loop is among GROUPs of contiguous elements. Iterations for the two nested level loops are independent, offering a potential parallelism with the OpenMP library. Performance gain obtained show that the parallelization of the outer loop with the standard OpenMP library achieves high performance gain comparable to those obtained by XKAAPI library. Then, we discuss the limitations of the standard OpenMP library to handle with load balancing for nested parallelism. We propose a new loop scheduler that ensures load balancing between different nested levels while respecting the hierarchy of the parallel platform. Performance gain obtained by several cases study, proves that to get an optimal load balancing with our scheduler we should opt for a constrained scheduling for the different nested levels.
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Submitted on : Monday, January 9, 2017 - 11:35:58 PM
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  • HAL Id : tel-01430501, version 1



Marwa Sridi. Un modèle de structure de données Cache-aware pour un parallélisme et un équilibrage dynamique de la charge. Informatique [cs]. Université de Grenoble Alpes, 2016. Français. ⟨tel-01430501⟩



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