Modulateur ΣΔ Complexe Passe-Bande à Temps-Continu pour la Réception Multistandard

Abstract : The research that we present in this thesis is in the field of circuit design and systems for scanning multi-standard wideband radio signals. The purpose of this work is the development of new methodologies for the design of analog and mixed VLSI circuits, and low consumption for analog-digital converter (ADC). We propose the use of a complex type continuous-time ΣΔ ADC bandpass for Low-IF architecture. This allows to simplify the analog stage baseband dodging the need for circuits such as the automatic gain controller, the anti-aliasing filter, and filters image rejection. The receiver is more linear and has an adequate degree of integrability for multistandard software radio applications Type Restricted (SDR). The first contribution is to provide an original and fully automated methodology ΣΔ modulator design for reception SDR. A new stabilization strategy based on the placement of the zeros and poles of the loop filter is developed allowing to simplify the passage of time-discrete to continuous-time with a simple correspondence between the areas for integrators and resonators the loop filter. The second contribution is the construction of a generic architecture of the ΣΔ modulator complex continuous-time following an original methodology. The basic elements of this architecture are the two low-pass ΣΔ modulators for I and Q channels in time-continuous. Both filters loops are cross coupled in the polyphase structure, allowing the shift to the intermediate frequency of the receiver. We designed a sizing tool for MATLAB modulators ΣΔ multistandard stable high order continuous-time, low pass, band pass real and complex. The third contribution of this work relates to the proposal for an advanced design methodology VLSI circuits for mixed type ΣΔ ADCs. This design methodology allows a combination of the downlink approaches' Top-down and uplink 'bottom-up', which makes it possible to analyze the design compromises by the concurrent use of the transistor-level circuits and behavioral models. This approach allows to combine both the accuracy and speed of process simulation during the design type of ΣΔ ADCs. Behavioral modeling of the ΣΔ modulator, using the VHDL-AMS language, has allowed us to developed a model library for the consideration of imperfections such as noise, jitter, the loop delay at the behavioral level. To illustrate the methodology proposed design, an example of the verification by the mixed simulation is provided through the design of a quantizer in CMOS technology. The extraction parameters imperfections diagram transistor level has made it possible to enrich the behavioral model and prevent abnormalities causing degradation ΣΔ modulator performance.
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  • HAL Id : tel-01260043, version 1


Nejmeddine Jouida. Modulateur ΣΔ Complexe Passe-Bande à Temps-Continu pour la Réception Multistandard. Micro et nanotechnologies/Microélectronique. Université Bordeaux 1 Sciences et Technologies; École Supérieure des Communications, Tunis, 2010. Français. ⟨tel-01260043⟩



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