N. Navet and F. Simonot-lion, Networked embedded system, Chapitre 13 Trends in Automotive Communication Systems, 2009.

H. Pham, Embedded computing architecture with dynamic hardware reconfiguration for intelligent automotive systems, 2010.

J. P. Calvez, Spécification et conception des systèmes : une méthodologie; Chapitre 3: Cycle de développement d'un système, 1992.

A. Sangiovanni-vincentelli, Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design, Proceedings of the IEEE, 2007.
DOI : 10.1109/JPROC.2006.890107

C. P. Luciano-lavano, Embedded systems. Chapitre3: Design of embedded systems, 2006.

M. Gries, Methods for evaluating and covering the design space during early design development The Embedded Microprocessor Benchmark Consortium, Integration, the VLSI Journal, vol.3820, issue.2, pp.131-183, 2004.

J. Schnerr, O. Bringmann, M. Krause, A. Viehl, and W. , Model-based design for embedded systems SystemC-based performance analysis of embedded systems, Chapitre P. J. M. Gabriela Nicolescu, vol.2, 2010.

A. Jantsch and I. Sander, Models of computation and languages for embedded system design, IEE Proceedings on computers and digital techniques, Special issue on embedded microeletronic systems, 2005.
DOI : 10.1049/ip-cdt:20045098

L. Gomes, J. P. Barros, and A. Costa, Embedded System Handbook, Chapitre 5: Modeling formalisms for embedded system design, 2006.

L. Lavagno, A. Sangiovanni-vincentelli, and E. Sentovich, System-Level Synthesis : Models of computation for embedded system design, 1998.

D. Harel and M. Politi, Modeling Reactive Systems With Statecharts, 1998.

A. Davare, A next-generation design framework for platform-based design, Design and Verification Conference, 2007.

G. Kahn, The semantics of simple language for parallel programming, proceedings of IFIP Congress, pp.471-475, 1974.

E. A. Lee and D. G. Messerschmitt, Synchronous data flow, Proceedings of the IEEE, vol.75, issue.9, pp.1234-1245, 1987.
DOI : 10.1109/PROC.1987.13876

P. Lieverse, P. Van-der-wolf, E. Deprettere, and K. Vissers, A Methodolology for Architecture Exploration of Heterogeneous Signal Processing Systems, IEEE Workshop on Signal Processing Systems, 1999.

A. D. Pimentel, C. Erbas, and S. Polstra, A systematic approach to exploring embedded system architectures at multiple abstraction levels, IEEE Transactions on Computers, vol.55, issue.2, 2006.
DOI : 10.1109/TC.2006.16

C. Erbas, A. D. Pimentel, M. Thompson, and S. Polstra, A Framework for System- Level Modeling and Simulation of Embedded Systems Architectures, EURASIP Journal on Embedded Systems, 2007.

A. D. Pimentel, The Artemis workbench for system-level performance evaluation of embedded systems, International Journal of Embedded Systems, vol.3, issue.3, pp.181-196, 2008.
DOI : 10.1504/IJES.2008.020299

C. Haubelt, A SystemC-Based Design Methodology for Digital Signal Processing Systems, EURASIP Journal on Embedded Systems, 2007.

W. Thomas, H. Andreas, and L. Gyoo-yeong, TAPES?Trace-based architecture performance evaluation with SystemC, pp.157-179, 2006.

J. Kreku, Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008.
DOI : 10.1109/JPROC.2006.890107

J. Kreku, K. Tiensyrjä, and G. Vanmeerbeeck, Automatic workload generation for system-level exploration based on modified GCC compiler, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010.
DOI : 10.1109/DATE.2010.5457175

T. Arpinen, E. Salminen, T. D. Hämäläinen, and M. Hännikäinen, Performance Evaluation of UML-2 Modeled Embedded Streaming Applications with System- Level Simulation, EURASIP Journal on Embedded Systems, 2009.

K. Tero, UML-Based Multiprocessor SoC Design Framework, ACM Transactions on Embedded Computing Systems (TECS), vol.5, issue.2, pp.281-320, 2006.

A. Viehl, B. Sander, O. Bringmann, and W. , Integrated requirement evaluation of non-functional system-on-chip properties, 2008 Forum on Specification, Verification and Design Languages, 2008.
DOI : 10.1109/FDL.2008.4641430

R. Dömer, System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design, EURASIP Journal on Embedded Systems, vol.4, issue.2, 2008.
DOI : 10.1109/TVLSI.2007.915390

G. Daniel, D. Rainer, P. Junyu, and G. Andreas, SpecC: Specification Language and Design Methodology, 2000.

F. Balarin, Metropolis: an integrated electronic system design environment, Computer, vol.36, issue.4, pp.45-52, 2003.
DOI : 10.1109/MC.2003.1193228

A. Sangiovanni-vincentelli, Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design, Proceedings of the IEEE, vol.95, issue.3, 2007.
DOI : 10.1109/JPROC.2006.890107

J. P. Calvez and G. Nicolescu, Spécification et validation des systèmes monopuces Chapitre 2: Spécification et modélisation des systèmes logiciels, 2004.

L. Cai and D. Gajski, Transaction level modeling: an overview, Proceedings of CODES+ISSS, 2003.

G. Schirner and R. Dömer, Quantitative analysis of the speed/accuracy trade-off in transaction level modeling, ACM Transactions on Embedded Computing Systems, vol.8, issue.1, pp.1-29, 2009.
DOI : 10.1145/1457246.1457250

F. Ghenassia, Transaction-level modeling with SystemC: TLM concepts and applications for embedded systems, 2005.
DOI : 10.1007/b137175

D. C. Black and J. Donovan, SystemC: From the Ground Up, 2004.

J. Peeters, N. Ventroux, T. Sassolas, and L. Lacassagne, A systemc TLM framework for distributed simulation of complex systems with unpredictable communication, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011.
DOI : 10.1109/DASIP.2011.6136847

N. Savoiu, S. K. Shukla, and R. Gupta, Automated concurrency re-assignment in high level system models for efficient system-level simulation, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, 2002.
DOI : 10.1109/DATE.2002.998404

G. Schirner and R. Dömer, Result-Oriented Modeling—A Novel Technique for Fast and Accurate TLM, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.9, 2007.
DOI : 10.1109/TCAD.2007.895757

M. Radetzki and R. S. Khaligh, Accuracy-Adaptive Simulation of Transaction Level Models, Europe, p.8, 2008.

R. , S. Khaligh, and M. Radetzki, A latency, preemption and data transfer accurate adaptive transaction level model for efficient simulation of pipelined buses, proceedings of Forum on specification and Design Languages (FDL), 2008.

M. Karner, C. Steger, R. Weiss, and E. Armengaud, Optimizing HW/SW Cosimulation based on run-time model switching," in proceeding of Forum specification and design languages FDL, 2009.

J. P. Calvez, Embedded real-time systems, P. Wiley Series In Software Engineering, 1993.

A. Barreteau, Techniques de modélisation transactionnelle pour le dimensionnement des futurs systèmes de radiocommunication mobiles, Ecole doctorale Sciences et technologies de l'information et mathématiques Thèse ED 503-116, 2010.

P. Tanguy, Etude et optimisations d'une communication à haut débit par courant porteur en ligne pour l'automobile, 2012.

. Homeplug-powerline-alliance, . Av-white, and . Paper, [Online]. www.homeplug.org [63] I. Powerline Alliance, 2005.

T. Majdoub, S. Le-nours, O. Pasquier, and F. Nouvel, Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011.
DOI : 10.1109/DASIP.2011.6136848
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