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Safe Design Method of COTS based embedded systems based on COTS

Abstract : Abstract This PhD dissertation contributes to the safe design of COTS-based control-command embedded systems. Due to design constraints bounding delays, costs and engineering resources, component re-usability has become a key issue in embedded design. The major difficulty in designing these systems is the high number of COTS components, which usually are separately built. The design process amounts to assembling these elementary components; this often establishes a certain amount of interaction between sets components which were not initially intended to interact with each others. Thus, unwanted behaviors may occur, although each component taken separately is considered free of local errors. The challenge that the designer faces is to ensure a safe behavior of the system which is built over the COTS components. Our proposal is a design method which ensures correction of COTS-based designs. This method uses in synergy a number of design techniques and tools. It starts from modeling of the COTS components which are stored in a generic COTS library, and ends with a design of the global control-command system, verified to be free of errors and ready to be implemented over a hardware chip such as an ASIC or an FPGA "Field Programmable Gate Array". The designer starts by modeling the temporal and logical local preconditions and postconditions of each COTS component, then the global pre/post conditions of the assembly which are not necessary a simple combination of local properties. He models also a list of properties that must be satisfied by the assembly. Any violation of these properties is defined as a design error. Then, by using the model checking approach the model of the assembly is verified against the predefined local and global properties. Some design errors can be corrected automatically through the Discrete Controller Synthesis method (DCS), others however must be manually corrected. After the correction step, the controlled control-command system is verified. Finally a global simulation step is proposed in order to perform a system-level verification beyond the capabilities of available formal tools. A human intellectual intervention in this design method appears is the intermediate step between detecting the errors and correcting them automatically. The model checking technique can only discover the errors and provide a counterexample which indicates where and how a property was violated, however, it leaves the correction task to the designer. On the other hand, DCS can correct errors by generating a “correct-by-construction” patch which controls the bugged component by assigning a subset of its inputs, designated as “controllable”. Despite its obvious advantages, the brute force application of this operation is completely unnatural to embedded designers. We propose to use the model-checking counterexample as a hint for guiding the application of DCS. Thus, our study combines three design techniques: the formal verification, the discrete controller synthesis and simulation, in order to provide a system safe by construction with the minimum manual interaction, to avoid making human mistakes in the design. We mention the advantages of each technique and argue its disadvantages and explain how each one is necessary for the others to provide an integrated work. We apply the method on two different systems, one concerns transferring data from senders to receivers through FIFO unit, the other is controlcommand system of a train passengers’ access.
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Contributor : Salam Hajjar <>
Submitted on : Tuesday, November 4, 2014 - 2:31:46 PM
Last modification on : Monday, September 13, 2021 - 2:44:03 PM
Long-term archiving on: : Thursday, February 5, 2015 - 10:11:17 AM


  • HAL Id : tel-01079889, version 1


S. Hajjar. Safe Design Method of COTS based embedded systems based on COTS. Automatic Control Engineering. INSA de Lyon, 2013. English. ⟨tel-01079889⟩



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