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	1 2 3 4 5 6 7 8 9 10	Pertinence Auteur A→Z Auteur Z→A Titre A→Z Titre Z→A Date de publication croissante Date de publication décroissante Date de dépôt croissante Date de dépôt décroissante 30 résultats par page 50 résultats par page 100 résultats par page Pour les 353 documents Exporter XML-TEI BibTeX EndNote CSV PDF Export avancé... Syndication RSS ATOM
	lirmm-00137598v1 Communication dans un congrès Luigi Dilillo, Paul Rosinger, Patrick Girard, Bashir Al-Hashimi. Minimizing Test Power in SRAM through Pre-charge Activity Reduction SIGDA ACM Press. DATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. ACM/IEEE, Design, Automation and Test in Europe Conference and Exhibition, pp.1159-1165, 2006, <10.1109/DATE.2006.244016>
	lirmm-01457424v1 Communication dans un congrès Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan. An effective BIST architecture for power-gating mechanisms in low-power SRAMs ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. IEEE, 17th International Symposium on Quality Electronic Design, pp.185-191, 2016, <http://www.isqed.org/English/Archives/2016/>. <10.1109/ISQED.2016.7479198>
	lirmm-01457396v1 Communication dans un congrès Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi et al. An effective approach for functional test programs compaction DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2016, <http://ddecs2016.fiit.stuba.sk/DDECS_2016/>. <10.1109/DDECS.2016.7482466>
	lirmm-01457361v1 Communication dans un congrès Alberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka et al. Auto-adaptive ultra-low power IC DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. IEEE, 11th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016, <http://www.dtis2016.teiath.gr>. <10.1109/DTIS.2016.7483886>
	lirmm-01456983v1 Poster Carolina Metzler, Aida Todri-Sanial, Patrick Girard. Small Delay Defect Investigation in Critical Path Delay with Multiple TSVs EMicro-NE, Oct 2015, Campina Grande, Brazil. X Escola de Microeletrônica do Nordeste, 2015, <https://sites.google.com/site/emicrone2015/>
	lirmm-01446917v1 Communication dans un congrès Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi et al. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016, <10.1109/ISVLSI.2016.42 >
	lirmm-01446887v1 Article dans une revue Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet et al. An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization Journal of Electronic Testing, Springer Verlag, 2016, 32 (6), pp.721-733. <10.1007/s10836-016-5621-1>
	lirmm-01446854v1 Communication dans un congrès Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A hybrid power modeling approach to enhance high-level power models DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems, 2016, <http://ddecs2016.fiit.stuba.sk/DDECS_2016/>. <10.1109/DDECS.2016.7482453>
	lirmm-01255754v1 Article dans une revue Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo et al. Globally Constrained Locally Optimized 3-D Power Delivery Networks IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144. <10.1109/TVLSI.2013.2283800>
	hal-01444734v1 Communication dans un congrès Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard et al. A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. 21th IEEE European Test Symposium, 2016, <http://www.ets16.nl/>. <10.1007/s10836-017-5640-6>
	lirmm-00269337v1 Communication dans un congrès Yves Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Scan Cell Ordering for Low Power Scan Testing ETW: European Test Workshop, May 2002, Corfu, Greece. 7th IEEE European Test Workshop, 2002
	lirmm-00106515v1 Communication dans un congrès Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Hage-Hassan. Efficient Test of Dynamic Read Destructive Faults in SRAM Memories LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 6th IEEE Latin American Test Workshop, pp.40-45, 2005
	lirmm-00269529v1 Communication dans un congrès Yannick Bonhomme, Patrick Girard, L. Guiller, Christian Landrault, Serge Pravossoudovitch. Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint ITC: International Test Conference, Sep 2003, Charlotte, United States. pp.488-493, 2003, <10.1109/TEST.2003.1270874>
	lirmm-00806809v1 Communication dans un congrès João Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard et al. Impact of Resistive-Bridge Defects in TAS-MRAM Architectures ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. 21st IEEE Asian Test Symposium, pp.125-130, 2012, <10.1109/ATS.2012.37>
	lirmm-01433587v1 Direction d'ouvrage, Proceedings Aida Todri-Sanial, Giorgio Di Natale, Patrick Girard, Marc Belleville, Saraju P. Mohanty et al. Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI - 2015) Jul 2015, Montpellier, France. IEEE, 2015, 978-1-4799-8718-4. <www.isvlsi.org>
	lirmm-01433581v1 Direction d'ouvrage, Proceedings Saraju P. Mohanty, Nagarajan Ranganathan, Sanjukta Bhanja, Sandip Kundu, Patrick Girard et al. Proceeding of IEEE Computer Society Annual Symposium on VLSI (ISVLSI - 2014) Jul 2014, Tampa, FL, United States. 2014, 978-1-4799-3763-9. <http://www.eng.ucy.ac.cy/theocharides/isvlsi14>
	lirmm-01433571v1 Direction d'ouvrage, Proceedings Patrick Girard, Sybille Hellebrand, Zabo Peng, Matteo Sonza Reorda, Giorgio Di Natale. Proceedings of IEEE European Test Symposium (ETS - 2013) May 2013, Avignon, France. IEEE, 2013, 978-1-4673-6375-4. <http://www.ieee-ets.org/past_events/ets13/>
	lirmm-01433330v1 Communication dans un congrès Alberto Bosio, Patrick Girard, Arnaud Virazel. Test of Low Power Circuits: Issues and Industrial Practices ICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. 23rd IEEE International Conference on Electronics, Circuits and Systems, 2016, <http://icecs.isep.fr>
	lirmm-01433322v1 Communication dans un congrès Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A Cross-Level Power Estimation Technique to Improve IP Power Models Quality VLSI-SoC: Very Large Scale Integration-System-on-Chip, Sep 2016, Tallin, Estonia. 24th IFIP/IEEE International Conference on Very Large Scale Integration, 2016, <http://www.vlsi-soc.com>
	lirmm-01433308v1 Communication dans un congrès João Azevedo, Arnaud Virazel, Yuanqing Cheng, Alberto Bosio, Luigi Dilillo et al. Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects VALID: Advances in Systems Testing and Validation Lifecycle, Oct 2013, Venice, Italy. 5th International Conference on Advances in Systems Testing and Validation Lifecycle, pp.39-44, 2013, <https://www.iaria.org/conferences2013/VALID13.html>
	lirmm-01430859v1 Article dans une revue Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda et al. Scan-Chain Intra-Cell Aware Testing IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, PP (99), In press. <10.1109/TETC.2016.2624311>
	lirmm-01354754v1 Communication dans un congrès Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard. An Experimental Comparative Study of Fault-Tolerant Architectures VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. IARIA XPS Press, 7th International Conference on Advances in System Testing and Validation Lifecycle, pp.1-6, 2015, <http://www.iaria.org/conferences2015/VALID15.html>
	lirmm-01354746v1 Article dans une revue Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch et al. A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. <10.1007/s10836-016-5578-0>
	lirmm-01354745v1 Communication dans un congrès Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. An efficient hybrid power modeling approach for accurate gate-level power estimation ICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. 27th International Conference on Microelectronics, pp.17-20, 2015, <10.1109/ICM.2015.7437976>
	lirmm-00839062v1 Communication dans un congrès Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch et al. Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic Mode RADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. 14th European Conference on Radiation and Its Effects on Components and Systems, pp.1-4, 2013, <10.1109/RADECS.2013.6937429>
	lirmm-01272964v1 Article dans une revue Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch et al. Intra-Cell Defects Diagnosis Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.541-555. <10.1007/s10836-014-5481-5>
	lirmm-01272684v1 Communication dans un congrès Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel et al. Design-for-Diagnosis Architecture for Power Switches DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, 2015, <10.1109/DDECS.2015.18>
	lirmm-01272913v1 Communication dans un congrès Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni et al. Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology ISQED: International Symposium on Quality Electronic Design, Apr 2015, Santa Clara, United States. Quality Electronic Design (ISQED), 2015 16th International Symposium on, pp.366-370, 2015, <10.1109/ISQED.2015.7085453>
	lirmm-01272933v1 Communication dans un congrès Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard et al. An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.515-520, 2015, <10.1109/ISVLSI.2015.99>
	lirmm-01272937v1 Communication dans un congrès Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel et al. Exploring the impact of functional test programs re-used for power-aware testing DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280, 2015
	1 2 3 4 5 6 7 8 9 10	Pertinence Auteur A→Z Auteur Z→A Titre A→Z Titre Z→A Date de publication croissante Date de publication décroissante Date de dépôt croissante Date de dépôt décroissante 30 résultats par page 50 résultats par page 100 résultats par page Pour les 353 documents Exporter XML-TEI BibTeX EndNote CSV PDF Export avancé... Syndication RSS ATOM

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