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hal-00564558v1
Chapitre d'ouvrage
O. Elissati, E. Yahya, Laurent Fesquet, S. Rieubon. Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer, pp.137-149, 2010, Lecture Notes in Computer Science, Vol. 6448 |
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hal-00016113v1
Chapitre d'ouvrage
K. Slimani, J. Fragoso, Laurent Fesquet, Marc Renaudin. Low Power Asynchronous Processors Low-Power Electronics Design, CRC Press, 912p., Chapter 22; Volume: 1, 2004, Series: Computer Engineering |
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hal-00841614v1
Communication dans un congrès
T. Le Pelleter, T. Beyrouthy, Y. Leroy, A. Bonvilain, R. Rolland et al. Low-power signal processing platform based on non-uniform sampling and event-driven circuitry Design, Automation and Test in Europe (DATE'13), Mar 2013, Grenoble, France. 2013, University Booth |
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hal-00646564v1
Communication dans un congrès
K. Alsayeg, Laurent Fesquet, G. Sicard, Marc Renaudin. A modular synthesis method for low-power QDI state machines 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. IEEE Computer Society, pp.185 - 188, 2011, <10.1109/NEWCAS.2011.5981286> |
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hal-00009604v1
Communication dans un congrès
E. Allier, Laurent Fesquet, Marc Renaudin, G. Sicard. Low-power asynchronous A/D conversion Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science, 2002, Séville, Spain. Springer Verlag, pp.81-91, 2002, Vol.2451 |
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hal-00009603v1
Communication dans un congrès
M.E. Salhiene, Laurent Fesquet, Marc Renaudin. Dynamic voltage scheduling for real time asynchronous systems Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science-, 2002, Séville, Spain. Springer Verlag, pp.390-9, 2002, Vol.2451 |
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hal-00009583v1
Communication dans un congrès
E. Allier, G. Sicard, Laurent Fesquet, Marc Renaudin. A new class of asynchronous A/D converters based on time quantization Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems, 2003, Vancouver, BC, Canada. IEEE, pp.196-205, 2003, BOOK NUMBER: 0769518982. <10.1109/ASYNC.2003.1199179> |
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hal-01393420v1
Communication dans un congrès
C. Al Khatib, C. Aupetit, C. Chevalier, C. Aktouf, G. Sicard et al. A Generic Clock Controller for Low Power Systems: Experimentation on an AXI Bus IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'15) , Oct 2015, Daejeon, North Korea. IEEE, Proceedings |
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