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lirmm-01272986v1  Article dans une revue
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel et al.  Design for Test and Diagnosis of Power Switches
Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.1640013. <10.1142/S0218126616400132>
lirmm-01248596v1  Communication dans un congrès
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard et al.  Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration
ASP-DAC: Asia and South Pacific Design Automation Conference, Jan 2014, Singapore, Singapore. pp.544-549, 2014, Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific. <10.1109/ASPDAC.2014.6742948>
lirmm-01248598v1  Communication dans un congrès
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard et al.  Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.223-225, 2014, <10.1109/DDECS.2014.6868794>
lirmm-01248597v1  Communication dans un congrès
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et al.  A Comprehensive Evaluation of Functional Programs for Power-Aware Test
NATW: North Atlantic Test Workshop, May 2014, Johnson City, NY, United States. IEEE, Test Workshop (NATW), 2014 IEEE 23rd North Atlantic, pp.69-72, 2014, <10.1109/NATW.2014.23>
lirmm-01248617v1  Communication dans un congrès
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard et al.  A novel method to mitigate TSV electromigration for 3D ICs
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. pp.121-126, 2013, <10.1109/ISVLSI.2013.6654633>
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lirmm-00326800v1  Chapitre d'ouvrage
Patrick Girard, Xiaoqing Wen, Nur Touba. Low Power Testing
Morgan Kaufmann. System-on-Chip Test Architectures: Nanometer Design for Testability, pp.207-350, 2007, 978-0-12-373973-5
lirmm-01446917v1  Communication dans un congrès
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi et al.  Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016, <10.1109/ISVLSI.2016.42 >
lirmm-01446854v1  Communication dans un congrès
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. A hybrid power modeling approach to enhance high-level power models
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th International Symposium on Design and Diagnostics of Electronic Circuits Systems, 2016, <http://ddecs2016.fiit.stuba.sk/DDECS_2016/>. <10.1109/DDECS.2016.7482453>
lirmm-00805140v1  Communication dans un congrès
Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et al.  Test Solution for Data Retention Faults in Low-Power SRAMs
EDA Association. DATE: Design, Automation and Test in Europe, Mar 2013, Grenoble, France. Design, Automation & Test in Europe Conference & Exhibition, pp.442-447, 2013, <http://www.date-conference.com/>. <10.7873/DATE.2013.099>
lirmm-00805143v1  Communication dans un congrès
Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et al.  Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions
ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. IEEE, pp.1-10, 2012, <http://www.itctestweek.org/>. <10.1109/TEST.2012.6401578>
lirmm-01433330v1  Communication dans un congrès
Alberto Bosio, Patrick Girard, Arnaud Virazel. Test of Low Power Circuits: Issues and Industrial Practices
ICECS: International Conference on Electronics, Circuits and Systems, Dec 2016, Monte Carlo, Monaco. 23rd IEEE International Conference on Electronics, Circuits and Systems, 2016, <http://icecs.isep.fr>
lirmm-00818984v1  Communication dans un congrès
Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel. Why and How Controlling Power Consumption During Test: A Survey
ATS: Asian Test Symposium, Nov 2012, Niigata, Japan. Test Symposium (ATS), 2012 IEEE 21st Asian, pp. 221-226, 2012, <http://aries3a.cse.kyutech.ac.jp/~ats12/>. <10.1109/ATS.2012.30>
lirmm-01457361v1  Communication dans un congrès
Alberto Bosio, Philippe Debaud, Patrick Girard, Stéphane Guilhot, Miroslav Valka et al.  Auto-adaptive ultra-low power IC
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2016, Istanbaul, Turkey. IEEE, 11th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016, <http://www.dtis2016.teiath.gr>. <10.1109/DTIS.2016.7483886>
lirmm-01457396v1  Communication dans un congrès
Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi et al.  An effective approach for functional test programs compaction
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. IEEE, 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2016, <http://ddecs2016.fiit.stuba.sk/DDECS_2016/>. <10.1109/DDECS.2016.7482466>
lirmm-01457424v1  Communication dans un congrès
Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan. An effective BIST architecture for power-gating mechanisms in low-power SRAMs
ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. IEEE, 17th International Symposium on Quality Electronic Design, pp.185-191, 2016, <http://www.isqed.org/English/Archives/2016/>. <10.1109/ISQED.2016.7479198>
lirmm-01248590v1  Communication dans un congrès
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel et al.  Test and diagnosis of power switches
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.213-218, 2014, <10.1109/DDECS.2014.6868792>
lirmm-00805123v1  Communication dans un congrès
Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch et al.  Failure Analysis and Test Solutions for Low-Power SRAMs
ATS: Asian Test Symposium, Nov 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.459-460, 2011, <http://www.ecs.umass.edu/ece/ats11/>. <10.1109/ATS.2011.97>
lirmm-00805366v1  Communication dans un congrès
Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et al.  A Built-in Scheme for Testing and Repairing Voltage Regulators of Low-Power SRAMs
VTS: VLSI Test Symposium, Apr 2013, Berkeley, CA, United States. pp.1-6, 2013, VLSI Test Symposium (VTS), 2013 IEEE 31st. <http://www.tttc-vts.org/public_html/new/2013/index.php>. <10.1109/VTS.2013.6548894>
lirmm-00805374v1  Communication dans un congrès
Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial et al.  Defect Analysis in Power Mode Control Logic of Low-Power SRAMs
ETS: European Test symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, 2012, <http://ets2012.imag.fr/>. <10.1109/ETS.2012.6233033>
hal-01444734v1  Communication dans un congrès
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard et al.  A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. 21th IEEE European Test Symposium, 2016, <http://www.ets16.nl/>. <10.1007/s10836-017-5640-6>
lirmm-01248599v1  Communication dans un congrès
Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard et al.  Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.207-212, 2014, <10.1109/DDECS.2014.6868791>
lirmm-01248601v1  Communication dans un congrès
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri-Sanial, Arnaud Virazel et al.  iBoX — Jitter based Power Supply Noise sensor
ETS: European Test Symposium, May 2014, Paderborn, United States. Test Symposium (ETS), 2014 19th IEEE European, pp.1-2, 2014, <10.1109/ETS.2014.6847830>
lirmm-01272937v1  Communication dans un congrès
Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel et al.  Exploring the impact of functional test programs re-used for power-aware testing
DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. pp.1277-1280, 2015
lirmm-01272735v1  Communication dans un congrès
Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture
IOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, pp.89-94, 2015, <http://tima.imag.fr/conferences/iolts/iolts15/>. <10.1109/IOLTS.2015.7229838>
lirmm-01272684v1  Communication dans un congrès
Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel et al.  Design-for-Diagnosis Architecture for Power Switches
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2015, Belgrade, Serbia. pp.43-48, 2015, <10.1109/DDECS.2015.18>
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lirmm-01354745v1  Communication dans un congrès
Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier. An efficient hybrid power modeling approach for accurate gate-level power estimation
ICM: International Conference on Microelectronics, Dec 2015, Casablanca, Morocco. 27th International Conference on Microelectronics, pp.17-20, 2015, <10.1109/ICM.2015.7437976>
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lirmm-00806774v1  Article dans une revue
Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 21 (5), pp.958-970. <10.1109/TVLSI.2012.2197427>
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lirmm-01255754v1  Article dans une revue
Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo et al.  Globally Constrained Locally Optimized 3-D Power Delivery Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2014, 22 (10), pp.2131-2144. <10.1109/TVLSI.2013.2283800>
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