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hal-00016113v1
Chapitre d'ouvrage
K. Slimani, J. Fragoso, Laurent Fesquet, Marc Renaudin. Low Power Asynchronous Processors Low-Power Electronics Design, CRC Press, 912p., Chapter 22; Volume: 1, 2004, Series: Computer Engineering |
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hal-00646564v1
Communication dans un congrès
K. Alsayeg, Laurent Fesquet, G. Sicard, Marc Renaudin. A modular synthesis method for low-power QDI state machines 9th IEEE International NEWCAS Conference, Jun 2011, Bordeaux, France. IEEE Computer Society, pp.185 - 188, 2011, <10.1109/NEWCAS.2011.5981286> |
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hal-00009604v1
Communication dans un congrès
E. Allier, Laurent Fesquet, Marc Renaudin, G. Sicard. Low-power asynchronous A/D conversion Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science, 2002, Séville, Spain. Springer Verlag, pp.81-91, 2002, Vol.2451 |
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hal-00009603v1
Communication dans un congrès
M.E. Salhiene, Laurent Fesquet, Marc Renaudin. Dynamic voltage scheduling for real time asynchronous systems Integrated-Circuit-Design.-Power-and-Timing-Modeling,-Optimization-and-Simulation.-12th-International-Workshop,-PATMOS-2002.-Proceedings-Lecture-Notes-in-Computer-Science-, 2002, Séville, Spain. Springer Verlag, pp.390-9, 2002, Vol.2451 |
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hal-00009583v1
Communication dans un congrès
E. Allier, G. Sicard, Laurent Fesquet, Marc Renaudin. A new class of asynchronous A/D converters based on time quantization Proceedings-Ninth-International-Symposium-on-Asynchronous-Circuits-and-Systems, 2003, Vancouver, BC, Canada. IEEE, pp.196-205, 2003, BOOK NUMBER: 0769518982. <10.1109/ASYNC.2003.1199179> |
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hal-00222098v1
Communication dans un congrès
D. Rios, Bertrand Folco, Y. Monnet, Marc Renaudin. Power consumption profile analysis of asynchronous QDI circuits 6ème journées d'études Faible Tension Faible Consommation (FTFC'07), May 2007, Paris, France. ISEP, Paris, France, pp.81-85, 2007 |
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hal-00096996v1
Communication dans un congrès
Ghislain Bouesse, Marc Renaudin, A. Witon, F. Germain. A clock-less low-voltage AES crypto-processor Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European, 2005, Grenoble, France. IEEE, pp.403- 406, 2005, <10.1109/ESSCIR.2005.1541645> |
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hal-00142378v1
Communication dans un congrès
Ghislain Bouesse, G. Sicard, Marc Renaudin. Path swapping method to improve DPA resistance of QDI asynchronous circuits L. Goubin, M. Matsui. 2006, Springer Verlag, Berlin, Germany, pp.384-398, 2006, LNCS 4249 |
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hal-00107405v1
Communication dans un congrès
D. Caucheteux, E. Beigne, Marc Renaudin, E. Crochon. AsyncRFID: fully asynchronous contactless systems, providing high data rates, low power and dynamic adaptation 12th IEEE International Symposium on Asynchronous Circuits and Systems, Mar 2006, Grenole, France. IEEE, pp.86-95, 2006, <10.1109/ASYNC.2006.12> |
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hal-00009567v1
Communication dans un congrès
Ghislain Bouesse, Marc Renaudin, S. Dumont, F. Germain. DPA on quasi delay insensitive asynchronous circuits: formalization and improvement EDAA. DATE'05, Mar 2005, Munich, Germany. 1, pp.424 - 429, 2005, <10.1109/DATE.2005.124> |
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hal-00009609v1
Communication dans un congrès
C. Piguet, Marc Renaudin, T.-J.-F. Omnes. Special session on low-power systems on chips (SOCs) Proceedings-Design,-Automation-and-Test-in-Europe.-Conference-and-Exhibition-2001., 2001, Munich, Germany. IEEE, pp.488-94, 2001, <10.1109/DATE.2001.915068> |
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hal-00672355v1
Article dans une revue
F. Abouzeid, S. Clerc, F. Firmin, Marc Renaudin, G. Sicard. 40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2011, 16 (3), pp.article 35. <10.1145/1970353.1970369> |
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hal-00144715v1
Article dans une revue
D. Rios, A. Buhrig, G. Sicard, Marc Renaudin. On the use of feedback control to dynamically control the supply voltage of low-power circuits Journal of Low Power Electronics, American Scientific Publishers, 2006, 2, N°1, pp.45?55. <10.1166/jolpe.2006.006> |
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