FPGA-based platform for fast accurate evaluation of Ultra Low Power SoC

Guillaume Patrigeon (1) , Pascal Benoit (1) , Lionel Torres (1)

1 ADAC - ADAptive Computing

Accurate evaluation of Ultra Low Power Systems on Chip (ULP SoC) is a huge challenge for designers and developers. In embedded applications, especially for Internet of Things end-node devices, ULP SoCs have to interact with their environment and need self-management. For this kind of applications, modelling a complete SoC, including processor(s), memories, all the peripherals components, their interaction and low-power policies, can be very complex in terms of developments and benchmarking. In order to cope with this challenge, an approach is to implement the desired system on FPGA with a monitoring infrastructure dedicated to fast and accurate performance evaluation. In this paper, we propose a set of different tools used during the evaluation step that can also be easily implemented on the final product and used by the system itself for self-assessment to enable adaptive behaviour. Illustrated by a simple architecture implemented on an FPGA-based platform, this method brings flexible, cycle accurate, fast and reliable performance evaluation and self-evaluation, with the possibility to use the platform for low-cost prototyping.

Mots clés: FPGA; Cortex-M0; Performance evaluation; Cycle accurate; Self-monitoring

Domaines: Micro et nanotechnologies/Microélectronique

Guillaume Patrigeon, Pascal Benoit, Lionel Torres. FPGA-based platform for fast accurate evaluation of Ultra Low Power SoC. PATMOS: Power and Timing Modeling, Optimization and Simulation, Jul 2018, Platja d'Aro, Spain. pp.123-128, ⟨10.1109/PATMOS.2018.8464173⟩. ⟨lirmm-01890567⟩