Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption

Mathieu da Silva (1) , Marie-Lise Flottes (1) , Giorgio Di Natale (1) , Bruno Rouzeyre (1)

1 TEST - Test and dEpendability of microelectronic integrated SysTems

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular, secret keys used by the device for data encryption/decryption in mission mode. This paper presents a scan attack countermeasure based on the encryption of the data written to or read from the scan chains. The secret-key management system already embedded in the device is used to provide appropriate keys for encryption of data flowing on the scan chains. The goal of the proposed solution is to counteract the scan-related security threats while preserving test and diagnosis efficiency provided by conventional design-for-testability techniques, as well as to allow debugging capabilities in mission mode. The proposed solution can deal with both stuck-at and transition-faults test schemes as well as single and multiple scan chain configurations using test data compression schemes. We will show that the proposed scheme provides expected test/diagnostic and debug facilities as classical scan design with marginal impacts on area, test time and design flows, while successfully preventing control and observation of data flowing in the scan chains by unauthorized users.

Mots clés: Design-for-Testability; Test and Security; Scan Attacks Countermeasure; Lightweight Encryption

Domaines: Micro et nanotechnologies/Microélectronique

Mathieu da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, 38 (3), pp.538-550. ⟨10.1109/TCAD.2018.2818722⟩. ⟨lirmm-01867245⟩