An intra-cell defect grading tool

Alberto Bosio (1) , Luigi Dilillo (1) , Patrick Girard (1) , Aida Todri-Sanial (2) , Stefano Bernabovi (3) , Paolo Bernardi (3)

1 TEST - Test and dEpendability of microelectronic integrated SysTems
2 SmartIES - Smart Integrated Electronic Systems
3 Dipartimento di Elettronica

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

Mots clés: Test; Intra-cell defect; Fault simulation; Diagnosis; Dictionaries; Logic gates; Databases; continuous scaling; intra-cell defect grading tool; Circuit faults; Automatic test pattern generation; Transistor size; intra-cell diagnosis resolution; Intra-cell defects; scaling circuits; applied test set; integrated circuit testing; flip-flops; Integrated circuit modeling; Libraries

Domaines: Micro et nanotechnologies/Microélectronique

Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Stefano Bernabovi, et al.. An intra-cell defect grading tool. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.298-301, ⟨10.1109/DDECS.2014.6868814⟩. ⟨lirmm-01248591⟩