Hardware Trojan Prevention using Layout-Level Design Approach

Papa-Sidy Ba (1) , Manikandan Palanichamy (2) , Sophie Dupuis (1) , Marie-Lise Flottes (1) , Giorgio Di Natale (1) , Bruno Rouzeyre (1)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention techniques through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.

Domaines: Micro et nanotechnologies/Microélectronique

Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩. ⟨lirmm-01234072⟩