Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Renan Alves Fonseca (1) , Luigi Dilillo (1) , Alberto Bosio (1) , Patrick Girard (1) , Serge Pravossoudovitch (1) , Arnaud Virazel (1) , Nabil Badereddine (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 Intel Mobile

We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.

Mots clés: SRAM; Core-cell; Test; Resistive-bridge defect; Fault modeling

Domaines: Electronique

Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. Journal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩. ⟨lirmm-00805017⟩