Setting Test Conditions for Improving SRAM Reliability

Renan Alves Fonseca (1) , Luigi Dilillo (2) , Alberto Bosio (2) , Patrick Girard (2) , Serge Pravossoudovitch (2) , Arnaud Virazel (2) , Nabil Badereddine (3)

1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
3 INFINEON - SOPHIA - Infineon Technologies France

In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible to detect SRAM core-cells with poor quality by applying a reduced set of test runs. The proposed methodology also allows determining the most appropriate DfT (Design-for-Test) technique for each peculiar SRAM design and technology.

Domaines: Micro et nanotechnologies/Microélectronique

Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Setting Test Conditions for Improving SRAM Reliability. ETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.257-262. ⟨lirmm-00492741⟩