Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory Array

Renan Alves Fonseca (1) , Luigi Dilillo (1) , Alberto Bosio (1) , Patrick Girard (1) , Serge Pravossoudovitch (1) , Arnaud Virazel (1) , Nabil Badereddine (2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 INFINEON - SOPHIA - Infineon Technologies France

In this paper, we present a study on the effects of resistive-bridging defects in the SRAM core-cell. In particular, the position of the resistive-bridges has been chosen taking in account an actual industrial core-cell layout. We have performed an extensive number of simulations, varying the resistance value of the defects, supply voltage, frequency and temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array. Static and dynamic faults, single-cell and double-cell faults have been found.

Domaines: Micro et nanotechnologies/Microélectronique

Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory Array. ETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009. ⟨lirmm-00433796⟩