Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA

Victor Lomné (1) , Philippe Maurine (2) , Lionel Torres (2) , Michel Robert (2) , Rafael Soares (3) , Ney Calazans (3) , Thomas Ordas (1)

1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
3 PUC-RS - Pontifícia Universidade Católica do Rio Grande do Sul [Brasil] = Pontifical Catholic University of Rio Grande do Sul [Brazil] = Université catholique pontificale de Rio Grande do Sul [Brésil]

Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.

Domaines: Micro et nanotechnologies/Microélectronique

Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, et al.. Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA. DATE: Design, Automation and Test in Europe, 2009, Nice, France. pp.634-639, ⟨10.1109/DATE.2009.5090744⟩. ⟨lirmm-00372847⟩