Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs
Résumé
As reported from industrial experiences, more than 50% of the system on Chip (SoC) area is nowadays used to embed different kinds of memory. This predominance of memories in SoC will grow up to 90% in the next few years, making memory malfunction the main detractor of SoC yield. Consequently, embedded memory testing is becoming more and more challenging and of crucial interest for SoC development. This study analyses the impact of technology scaling on defects and parameter deviations in embedded SRAMs. We first show how the impact of manufacturing defects may vary with the level of integration (130 nm down to 45 nm) of eSRAMs core-cell belonging to the same family. Secondly, we illustrate the effects of technology scaling (130 nm down to 45 nm) on device parameter variations. In the first part, we consider resistive-open defects in eSRAM core-cells as a case study. We demonstrate how technology scaling leads to dissimilarities in robustness of the core-cell and hence how it affects the faulty behavior of the memory. In the second part, we consider the variation of transistor threshold voltage (Vt mismatch) as a case study. We highlight the ceaseless increasing impact of these Vt mismatches on the correct behavior of the memory and how the behavior is affected depending on process corners, temperature and voltage. This work is a joined research work between LIRMM and Infineon Technologies. It has been funded by the French government under the framework of the MEDEA+ 2A702 "NanoTEST" European program.