Continuous Representation of the Performance of a CMOS Library

Benoit Lasbouygues (1) , J. Schindler (1) , Sylvain Engels (1) , Philippe Maurine (2) , Xavier Michel (3) , Nadine Azemard (2) , Daniel Auvergne (3)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
3 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

In a standard industrial approach the timing performance verification is obtained using a tabular method that necessitates a great amount of simulations. They must specify, for each drive in each logic family: the load, the input slope, the temperature and the supply voltage sensitivity, for each edge, of the transition time and propagation delay. Extending a logical effort like based model of timing performance of CMOS structures we show in this paper that it is possible to define a specific performance representation allowing a continuous representation of the performance sensitivity of a complete family. We describe the parameter calibration procedure and validate the proposed representation on a 0.13μm process by comparing the performance sensitivity deduced from this representation to sensitivity values obtained from electrical simulations performed with the full process model of the foundry

Domaines: Micro et nanotechnologies/Microélectronique

Benoit Lasbouygues, J. Schindler, Sylvain Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC: European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal. pp.595-598, ⟨10.1109/ESSCIRC.2003.1257205⟩. ⟨lirmm-00239459⟩