Skip to Main content Skip to Navigation
Conference papers

Evaluation of Design for Reliability Techniques in Embedded Flash Memories

Abstract : Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems ; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as Error Correction Code (ECC), Redundancy or Threshold Voltage (VT) Analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed.
Complete list of metadata
Contributor : Martine Peridier Connect in order to contact the contributor
Submitted on : Tuesday, December 11, 2007 - 2:53:20 PM
Last modification on : Friday, August 5, 2022 - 10:48:11 AM
Long-term archiving on: : Sunday, April 11, 2010 - 11:12:04 PM




Benoît Godard, Jean-Michel Daga, Lionel Torres, Gilles Sassatelli. Evaluation of Design for Reliability Techniques in Embedded Flash Memories. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.1593-1598, ⟨10.1109/DATE.2007.364529⟩. ⟨lirmm-00179951⟩



Record views


Files downloads