Scan design and secure chip [secure IC testing]

David Hely (1) , Marie-Lise Flottes (2) , Frédéric Bancel (3) , Bruno Rouzeyre (2) , Nicolas Berard , Michel Renovell (2)

1 INPG - Institut National Polytechnique de Grenoble
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
3 STMicroelectronics

Testing a secure system is often considered as a severe bottleneck. While testability requires to an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability techniques when designing secure ICs may seriously decrease the level of security provided by the chip. This dilemma is even more severe as secure applications need well-tested hardware to ensure that the programmed operations are correctly executed. In this paper, a security analysis of the scan technique is performed. This analysis aims at pointing out the security vulnerability induced by using such a DfT technique. A solution securing the scan is finally proposed.

Domaines: Micro et nanotechnologies/Microélectronique

David Hely, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Berard, et al.. Scan design and secure chip [secure IC testing]. IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.219-224, ⟨10.1109/OLT.2004.1319691⟩. ⟨lirmm-00108909⟩