Efficient Test of Dynamic Read Destructive Faults in SRAM Memories

Luigi Dilillo (1) , Patrick Girard (1) , Serge Pravossoudovitch (1) , Arnaud Virazel (1) , Magali Bastian Hage-Hassan (1, 2)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques
2 INFINEON - SOPHIA - Infineon Technologies France

This paper presents an analysis of the electrical origins of dynamic Read Destructive Faults (dRDFs) that affects the SRAM memories. This fault is the consequence of resistive-open defects in the refreshment loop of the SRAM core-cells. The consequence of this fault is that multiple consecutive read operations on a cell may induce the faulty swap of the stored value. In a recent paper, we have considered only two of the four possible dRDF fault primitives. Here, we complete this study by evaluating the effectiveness of all fault primitives. We also show that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect as an actual read operation for the dRDF sensitization. On this basis, we demonstrate that RESs can replace actual read operations in the dRDF fault primitives making them more efficient.

Domaines: Micro et nanotechnologies/Microélectronique

Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan. Efficient Test of Dynamic Read Destructive Faults in SRAM Memories. LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.40-45. ⟨lirmm-00106515⟩