Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Nabil Badereddine (1) , Patrick Girard (1) , Serge Pravossoudovitch (1) , Arnaud Virazel (1) , Christian Landrault (1)

1 SysMIC - Conception et Test de Systèmes MICroélectroniques

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we discuss a set of possible solutions to minimize peak power during all test cycles of a scan testing process. These solutions cover power-aware design solutions, scan chain stitching techniques and pattern modification heuristics.

Mots clés: Peak power; Clock cycle; Test pattern; Test cycle; Test vector

Domaines: Micro et nanotechnologies/Microélectronique

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault. Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.540-549, ⟨10.1007/11556930_55⟩. ⟨lirmm-00106111⟩