Performances and physical mechanisms in sub-0.1 µm gate length LDD MOSFETs at low temperature

F. Balestra , H. Nakabayashi , M. Tsuno , T. Matsumoto , M. Koyanagi

The electrical properties of sub-0.1 µm gate length LDD devices are investigated between room and liquid helium temperatures. The strong impact of gate overlapping effects on LDD resistance is shown for these ultra-short channel MOSFETs in a wide temperature range. It is experimentally demonstrated that these mechanisms lead to a substantial enhancement of the driving current when the devices are scaled down, and induce an additional improvement in the case of low temperature operation. Furthermore, the performances of these transistors with LDD structure at low temperature are also discussed in terms of field assisted impurity ionization in the LDD's.

Domaines: Articles anciens

F. Balestra, H. Nakabayashi, M. Tsuno, T. Matsumoto, M. Koyanagi. Performances and physical mechanisms in sub-0.1 µm gate length LDD MOSFETs at low temperature. Journal de Physique IV Proceedings, 1994, 04 (C6), pp.C6-13-C6-18. ⟨10.1051/jp4:1994602⟩. ⟨jpa-00253096⟩