Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology

Sébastien Le Beux (1) , Jelena Trajkovic (2) , Ian O'Connor (1) , Gabriela Nicolescu (3) , Guy Bois (4) , Pierre Paulin (5)

1 INL - CSH - INL - Conception de Systèmes Hétérogènes
2 GR2M - Groupe de recherche en microélectronique et microsystèmes
3 EPM - École Polytechnique de Montréal
4 GR2M - Groupe de recherche en microélectronique et microsystèmes
5 STMicroelectronics

State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising paradigms for the design of such next generation Multi-Processors System on Chip (MPSoC). They enable significantly increased bandwidth, increased immunity to electromagnetic noise, decreased latency, and decreased power. Therefore, defining new architectures taking advantage of optical interconnects represents today a key issue for MPSoC designers. Moreover, new design methodologies, considering the design constraints specific to these architectures are mandatory. In this paper, we present a contention-free new architecture based on optical network on chip, called Optical Ring Network-on-Chip (ORNoC). We also show that our network scales well with both large 2D and 3D architectures. For the efficient design, we propose automatic wavelength/waveguide assignment and demonstrate that the proposed architecture is capable of connecting 1296 nodes with only 102 waveguides and 64 wavelengths per waveguide.

Domaines: Architectures Matérielles [cs.AR]

Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, et al.. Optical Ring Network-on-Chip (ORNoC): Architecture and Design Methodology. Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2011, Grenoble, France. ⟨inria-00618600⟩