A. N. Choudhary and J. H. Patel, Parallel architectures and parallel algorithms for integrated vision systems, 1989.
DOI : 10.1007/978-1-4613-1539-1

B. Parhami, Introduction to Parallel Processing: Algorithms and Architectures, 1999.

R. and M. Hord, The Illiac IV: The First Supercomputer, 1982.
DOI : 10.1007/978-3-662-10345-6

W. D. Hillis, The Connection Machine, 1989.

M. Lee, H. Singh, G. Lu, N. Bagherzadeh, F. J. Kurdahi et al., Design and Implementation of the MorphoSys Reconfigurable Computing Processor, J. VLSI Signal Processing Systems, vol.24, pp.147-164, 2000.
DOI : 10.1007/978-1-4615-4417-3_3

M. Kumar and J. R. Jump, Performance enhancement in buffered delta networks using crossbar switches and multiple links, Journal of Parallel and Distributed Computing, vol.1, issue.1, pp.81-103, 1984.
DOI : 10.1016/0743-7315(84)90012-1

M. Rupp, D. Milojevic, and G. Gogniat, Design and Architectures for Signal and Image Processing, EURASIP J. on Embedded Systems, 2008.

T. H. Szymanski and V. C. Hamacher, On the universality of multipath multistage interconnection networks, Journal of Parallel and Distributed Computing, vol.7, issue.3, pp.541-569, 1989.
DOI : 10.1016/0743-7315(89)90035-X

C. P. Kruskal and M. Snir, A unified theory of interconnection network structure, Theoretical Computer Science, vol.48, pp.75-94, 1986.
DOI : 10.1016/0304-3975(86)90084-8

C. P. Kruskal and M. Snir, The Performance of Multistage Interconnection Networks for Multiprocessors, IEEE Transactions on Computers, vol.32, issue.12, pp.32-1091, 1983.
DOI : 10.1109/TC.1983.1676169

C. P. Kruskal, M. Snir, and A. Weiss, The distribution of waiting times in clocked multistage interconnection networks, IEEE Transactions on Computers, vol.37, issue.11, pp.1337-1352, 1988.
DOI : 10.1109/12.8700

D. H. Lawrie, Access and Alignment of Data in an Array Processor, IEEE Transactions on Computers, vol.24, issue.12, pp.1145-1155, 1975.
DOI : 10.1109/T-C.1975.224157

D. M. Dias and J. R. Jump, Analysis and Simulation of Buffered Delta Networks, IEEE Transactions on Computers, vol.30, issue.4, pp.273-282, 1981.
DOI : 10.1109/TC.1981.1675775

H. J. Siegel, Interconnection Networks for SIMD Machines, Computer, vol.12, issue.6, pp.57-65, 1979.
DOI : 10.1109/MC.1979.1658780

H. S. Stone, Parallel Processing with the Perfect Shuffle, IEEE Transactions on Computers, vol.20, issue.2, pp.153-161, 1971.
DOI : 10.1109/T-C.1971.223205

J. H. Patel, Performance of Processor-Memory Interconnections for Multiprocessors, IEEE Transactions on Computers, vol.30, issue.10, pp.771-780, 1981.
DOI : 10.1109/TC.1981.1675695

L. Benini and G. Demicheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921
URL : http://infoscience.epfl.ch/record/165542

M. C. Pease, The Indirect Binary n-Cube Microprocessor Array, IEEE Transactions on Computers, vol.26, issue.5, pp.458-473, 1977.
DOI : 10.1109/TC.1977.1674863

S. Ranka and S. Sanhi, Convolution on mesh connected multicomputers, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol.12, issue.3, pp.315-318, 1990.
DOI : 10.1109/34.49056
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.12.3325

A. Muhit, S. Md, M. Islam, and . Othman, VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression, Proc. International Conference on Autonomous Robots and Agents, p.4, 2004.

C. Hilton and B. Nelson, PNoC: a flexible circuit-switched NoC for FPGA-based systems, Proc. IEEE Computers and Digital Techniques, pp.181-188, 2006.
DOI : 10.1049/ip-cdt:20050175

C. Schack, W. Heenes, and R. Hoffmann, A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA, Proc. 9 th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.98-107, 2009.
DOI : 10.1007/978-3-540-73625-7_20

D. Parkinson, Experience in Using Highly Parallel Processing Using DAP, Proc. Massively Parallel Scientific Computation (NASA Conference Publication, pp.205-208, 1986.

F. Schurz and D. Fey, A Programmable Parallel Processor Architecture in FPGAs for Image Processing Sensors, Proc. Integrated Design and Process Technology, p.7, 2007.

H. C. Freitas and P. O. Navaux, Evaluating On-Chip Interconnection Architectures for Parallel Processing, 2008 11th IEEE International Conference on Computational Science and Engineering, Workshops, pp.188-193, 2008.
DOI : 10.1109/CSEW.2008.60

H. Du, M. Sanchez-elez, N. Tabrizi, N. Bagherzadeh, M. L. Anido et al., Interactive ray tracing on reconfigurable SIMD MorphoSys, Proc. Design, Automation and Test in Europe Conference, p.3, 2003.
DOI : 10.1007/0-306-48709-8_12
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.387.6323

H. J. Siegel and S. D. Smith, Study of multistage SlMD interconnection networks, Proc. 5 th annual Symp, pp.223-229, 1978.

M. Baklouti, . Ph, M. Marquet, J. Abid, and . Dekeyser, A design and an implementation of a parallel based SIMD architecture for SoC on FPGA, Proc. Design and Architectures for Signal and Image Processing DASIP, 2008.

R. Ferreira, M. Laure, A. C. Beck, T. Lo, M. Rutzig et al., A low cost and adaptable routing network for reconfigurable systems, 2009 IEEE International Symposium on Parallel & Distributed Processing, pp.1-8, 2009.
DOI : 10.1109/IPDPS.2009.5161217

R. Grondalski, A VLSI chip set for a massively parallel architecture, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, p.87, 1987.
DOI : 10.1109/ISSCC.1987.1157087

S. D. Smith and H. J. Siegel, An emulator network for SIMD machine interconnection networks, Proceedings of the 6th annual symposium on Computer architecture , ISCA '79, pp.232-241, 1979.
DOI : 10.1145/800090.802913

S. Duquennoy, S. L. Beux, . Ph, S. Marquet, J. Meftali et al., MpNoC Design: Modeling and Simulation, Proc. 15 th IP Based SoC Design Conference, 2006.

S. E. Eklund, A Massively Parallel Architecture for Linear Machine Code Genetic Programming, Proc. 4 th International Conference on Evolvable Systems: From Biology to Hardware, pp.216-224, 2001.
DOI : 10.1007/3-540-45443-8_19

T. Blank, The MasPar MP-1 architecture, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, pp.20-24, 1990.
DOI : 10.1109/CMPCON.1990.63648

X. Gao, Z. Zhang, and X. Long, Round Robin Arbiters for Virtual Channel Router, Proc. Multiconference on Computational Engineering in Systems Applications, pp.1610-1614, 2006.

Y. Aydi, S. Meftali, M. Abid, and J. Dekeyser, Dynamicity Analysis of Delta MINs for MPSOC Architectures, Proc. International Conference on Sciences ans Techniques of Automatic control and computer engineering, p.7, 2007.